module tx(clk,rst,Tx_en,tx_data,bps_clk,Tx_pin_out);
input clk,rst,Tx_en,bps_clk;
input[7:0] tx_data;
output Tx_pin_out;
reg[3:0] i;
reg tx;

always @(posedge clk or negedge rst)
begin
	if(!rst)
	begin
	i<=0;
	tx<=1;
	end
	else if(Tx_en)
		case(i)
			4'd0:if(bps_clk) begin i<=i+1'b1; tx<=1'b0; end
			4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8:
			if(bps_clk) begin i<=i+1'b1; tx<=tx_data[i-1]; end
			4'd9:if(bps_clk) begin i<=i+1'b1; tx<=1'b1; end
			4'd10:begin i<=i+1'b1; end
			4'd11:begin i<=0; end	
			endcase
end
assign Tx_pin_out=tx;

endmodule
